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Program Schedule
ISSM 2006 Schedule and Areas of Interest

ISSM 2006 Schedule
  • Factory Design (FD)
  • Manufacturing Control and Execution (MC)
  • Manufacturing Strategy and Structure (MS)
  • Process Control and Monitoring (PC)
  • Process and Metrology Equipment (PE)
  • Yield Enhancement Methodology (YE)
  • Ultraclean Technology (UC)
  • Environment, Safety and Health (ES)
  • Process and Material Optimization (PO)
  • Final Manufacturing (FM)
  • Robust Engineering (RE)

Note: Abstract of each paper will be available from the end of August by click on the presentation title.


Mon, Sep 25 | Tue, Sep 26 | Wed, Sep 27 | Interactive

8:30 Registration
9:40-10:00 Opening Remarks
Hajime Sasaki, Chairman, ISSM Organizing Committee/NEC
Michihiro Inoue, Chairman, ISSM Executive Committee/Panasonic
10:00-11:40 Plenary Session
Session Chair: Kensuke Uriga/Chairman, ISSM Program Committee/Dura Systems
10:00-10:50 Conquering Process Variability: A Key Enabler for Profitable Manufacturing in Advanced Technology Nodes
Andrzej.J. Strojwas Professor of Electrical and Computer Engineering, Carnegie Mellon Univ. Chief Technologist, PDF Solutions, Inc.
10:50-11:40 Collaboration in the 21st Century: Driving Innovation and Differentiation
Song Hwee Chia, President and Chief Executive Officer Chartered Semiconductor Manufacturing
11:40-13:00 Lunch Time
13:00-17:20 Session 1 (Room A)
Yield Enhancement Methodology(YE) & Environment, Safety and Health (ES)
13:00-13:20 YE-131
Watermark induced High Density Via failures in sub micron CMOS fabrication
Alex Chew Keng Chiow/Systems on Silicon Manufacturing
13:20-13:40 YE-198
In Situ Particle Monitors: The Next Level of Yield Control for Critical Processes
Ray Burghard/INFICON
13:40-14:00 YE-153
Voltage Comtrast Enhance for Gate Leak Failure Detected by Electron Beam Inspection
Katsuhiro Fujiyoshi/Renesas Technology
14:00-14:20 YE-126
Method of Minimizing Inspection Cost by Making Use of Programmed Defect Array
Takahide Hayano/Spansion
14:20-14:40
Authors' Interview Hours/Coffee Break
14:40-15:00 YE-197
Failure Mode Detection and Process Optimization for 65 nm CMOS Technology
Jeffrey R. D. DeBord/Texas Instruments
15:00-15:20 YE-200
Electrical Defect Density Test Structures for DFM in the Sub-wavelength Lithography Regime with Copper Metallization
Julie Segal/Spansion
15:20-15:40 YE-211
An Addressable Test Structure for Geometrical Design Rules Characterization
Hung-Jen Lin/Spansion
15:40-16:00 YE-217
Sample Effcient Regression Trees (SERT) for Yield Loss Analysis
Argon Chen/National Taiwan University
16:00-16:20
Authors' Interview Hours/Coffee Break
16:20-16:40 ES-69
Analysis and Risk Communication of 20 Years of Exposure Monitoring of Photolithography Solvents from all Intel Fabs
Harry A. Hunsaker/Intel
16:40-17:00 ES-122
Application of Atmospheric Plasma Abatement System for exhausted gas from MEMS etching process
Kenji Hattori/Taiyo Nippon Sanso Corporation
17:00-17:20
Authors' Interview Hours/Coffee Break
13:00-17:20 Session 2 (Room B)
Manufacturing Control and Execution (MC)
13:00-13:20 MC-221
Development of a Platform for Collaborative Engineering Data Flow between Design and Manufacturing
Hiroyuki Morinaga/Toshiba
13:20-13:40 MC-92
Risk Based Capacity Planning Method for Semiconductor Fab with Queue Time Constraints
Akira Ono/Renesas Technology
13:40-14:00 MC-231
Priority X-Factor Modeling for Differentiated Manufacturing Service Planning
Shi-Chung Chang/National Taiwan University
14:00-14:20 MC-80
300mm Time Constrained Queue Loop Management
David L. Van Sickle/Intel
14:20-14:40
Authors' Interview Hours/Coffee Break
14:40-15:00 MC-94
A Dynamic Method for Optimal WIP Allocation and Control in a Semiconductor Manufacturing System
Chih Ming Liu/National Tsing Hua University
15:00-15:20 MC-93
Supply Chain Inventory Control in Semiconductor Manufacturing
Ruey-Shan Guo/National Taiwan University
15:20-15:40 MC-60
Cycle Time Reduction Through Preventive Maintenance De-clustering
Mike Tao Zhang/Intel
15:40-16:00 MC-117
Conveyer Belt Model to Analyze Cycle Time Conditions in a Semiconductor Manufacturing Line
Toshikazu Inoue/Spansion
16:00-16:20
Authors' Interview Hours/Coffee Break
16:20-16:40 MC-179
Troubleshooting Tracks with Vibration Detection and Storage Technology.
Wahner, Lester J/Intel
16:40-17:00 MC-113
Increased Etch Chamber Productivity Through the Reduction of Unshceduled Wet Cleans
Brent Ames/Metron Technology
17:00-17:20 MC-48
Wire Bonder Mis-Process Reduction and Productivity Improvement Through Full Automation System: A Cross Regional Team Project
TAY CHAI THEAM/Texas Instruments
17:20-17:40
Authors' Interview Hours/Coffee Break
13:00-18:00 Session 3 (Room C)
Process Control and Monitoring (PC) Part 1
13:00-13:20 PC-176
The Future of CD Metrology
John Allgair/International Sematech
13:20-13:40 PC-90
Gate CD Control Considering Variation of Gate and STI Structure
Masaru Kurihara/Hitachi
13:40-14:00 PC-64
New Mechanism of LER Formation in Gate Process
Atsushi Yabata/Miyagi Oki Electric Co.,Ltd
14:00-14:20 PC-142
Development on the Highly Precise Detection System for the Abnormal Discharge at the Plasma Etching Equipment
Hirotoshi Ise/Renesas Technology
14:20-14:40
Authors' Interview Hours/Coffee Break
14:40-15:00 PC-215
Development of monitoring technology of ion implanter for particle detection
Satoshi Yasuda/Matsushita Electric (Panasonic)
15:00-15:20 PC-209
Device-level APC in Ion Implantation for Analog Device
takashi kyuho/Toshiba
15:20-15:40 PC-214
Fab-wide equipment monitoring and FDC system
Shin-ichi Imai/Matsushita Electric (Panasonic)
15:40-16:00 PC-49
Using a Z Tool Controller for APC Applications
Eugene Smith/Cypress Semiconductor
16:00-16:20
Authors' Interview Hours/Coffee Break
16:20-16:40 PC-83
Improvement of photolithography process by 2nd Generation Data Mining
Hidetaka Tsuda/Fujitsu LSI Technology Limited
16:40-17:00 PC-186
Enabling Double Patterning Lithography at the 32nm Node
Kevin Monahan/KLA-Tencor
17:00-17:20 PC-144
High sensitive focus monitoring on production wafer by Scatterometry Measurements for 90/65nm node devices.
Toshihide Kawachi/Renesas Technology
17:20-17:40 PC-247
Laser Scattering Microhaze Correlation with Polysilicon Surface Roughness and Impact on Electrical Performance
David K. Chen/KLA-Tencor


Mon, Sep 25 | Tue, Sep 26 | Wed, Sep 27 | Interactive

8:00 Regiration
9:00-10:40 Plenary Session Session
Chair: Kensuke Uriga/Chairman, ISSM Program Committee/Dura Systems
9:00-9:50 The CASMAT Business Model for Semiconductor Materials
Yoshifumi Kawamoto, Director, General Manager, R&D Department Consortium for Advanced Semiconductor Materials and Related Technologies (CASMAT)
9:50-10:40 Toshiba's Strategy in Semiconductor Business and Production Technology
Shozo Saito, Executive Vice President, Toshiba Semiconductor Company, Corporate Vice President, Toshiba Corporation
10:40-11:00
Coffee Break
11:00-14:40 Session 4 (Room A)
Process and Materials Optimization (PO)
11:00-11:20 PO-125
Advanced CD Control Technology for 65-nm Node Dual Damascene Process
Masatoshi Nagase/NEC Electronics
11:20-11:40 PO-148
Novel Deep SAC Etch Process Technology for advanced FCRAMTM*
Daisy Yang/SMIC
11:40-12:00 PO-246
Low Erosion Tungsten CMP Process with High Productivity
Masafumi Shiratani/NEC Electronics
12:00-12:20 PO-54
Elimination of Vmin failures in 0.15um logic process
Yee Ming Chan/Systems on Silicon Manufacturing
12:20-12:40
Authors' Interview Hours/Coffee Break
12:40-13:40
Lunch Time
13:40-14:00 PO-61
Impact on Latchup Immunity due to the Switch From Epitaxial to Bulk Substrate
Glen Foo Eu Gene/Systems on Silicon Manufacturing
14:00-14:20 PO-100
Analog Capacitor Integration Challenges
Xinfen Chen/Texas Instruments
14:20-14:40
Authors' Interview Hours/Coffee Break
11:00-14:40 Session 6 (Room B)
Ultraclean Technology (UC)
11:00-11:20 UC-116
Environmentally Friendly Single-Wafer Spin Cleaning Using Ultra-diluted HF/nitrogen Jet Spray without Causing Structural Damage and Material Loss
Hideki Hirano/Sony
11:20-11:40 UC-124
A Defect-Free Anodic Oxide Passivation for LSI/FPD Vacuum Chamber
Yasuhiro Kawase/Mitsubishi Chemical
11:40-12:00 UC-164
Wonderful new materials or yield killers? New metrics for metal contamination assessment
GABRIELA CATANA/IMEC
12:00-12:20 UC-123
Impact on Off-state Leakage Current in PMOS Device by Metallic Contamination
Young Seon You/Systems on Silicon Manufacturing
12:20-12:40 Authors' Interview Hours/Coffee Break
12:40-13:40
Lunch Time
13:40-14:40 Session 7 (Room B)
Factory Design/Automated Material Handling (FD)
13:40-14:00 FD-196
High Throughput AMHS Design with Dual Unified OHT System
ChungSoo Han/Spansion
14:00-14:20 FD-97
Requirements for AMHS in 450 mm era
Hiroshi Kondo/Asyst Shinko
14:20-14:40
Authors' Interview Hours/Coffee Break
11:00-12:20 Session 8 (Room C)
Process Control and Monitoring (PC) Part 2 & Robust Engineering (RE)
11:20-11:40 PC-250
A High Productivity and Low Topography WCMP Process with iScan and LAPC for 45nm
James C. Wang/Applied Materials
11:40-12:00 RE-62
Application of quality engineering in semiconductor wafer process
Shigenobu Murashima/NEC Kansai, Ltd
12:00-12:20
Authors' Interview Hours/Coffee Break
12:20-13:40
Lunch Time
13:20-15:40 Session 9 (Room C)
Final Manufacturing (FM)
13:40-14:20 Future Trend in Packaging Technology with View of the History
Prof. Kanji Otsuka Meisei University
14:20-14:40 Design For Business: Advancing the Business Culture of Semiconductor Back-End Manufacturing
Andres Carrasco/Nagase Electronic Equipment Service Co., Ltd.
14:40-15:00 FM-111
Advanced dicing technology for semiconductor wafer -Stealth Dicing-
Masayoshi Kumagai/Hamamatsu Photonics K.K.
15:00-15:20 FM-224
Root Cause Mechanism for Delamination/Cracking in Stacked Die Chip Scale Packages
Edward R. Prack/Intel
15:20-15:40
Authors' Interview Hours/Coffee Break


Mon, Sep 25 | Tue, Sep 26 | Wed, Sep 27 | Interactive

8:00 Registration
9:00-9:10 ISSM 2007
9:10-10:50 Plenary Session Session
Chair: Kensuke Uriga/Chairman, ISSM Program Committee/Dura Systems
9:10-10:00 Future Lithography Challenges
Kazuo Ushida, President, Precision Equipment Company, Nikon Corporation
10:00-10:50 The Strategy for Manufacturing Technology Advancement in Memory
Young-Bum Koh, Senior Vice President, Technology Center, Semiconductor Business, Samsung Electronics Co., Ltd.
10:50-11:10
Coffee Break
11:10-12:30 Session 10 (Room A)
Process and Materials Optimization (PO) Part 2
11:10-11:30 PO-109
Thin-Gate CMOS and Super-Thick Gate DECMOS Integration in 0 Degree On-axis <100> Staring Wafer: Process Challenges and Solutions
Xiaoju Wu/Texas Instruments
11:30-11:50 PO-119
Investigation on Metal Pillar Defect in sub-micron CMOS technology
Young Seon You/Systems on Silicon Manufacturing
11:50-12:10 PO-120
A criterion for applying countermeasure to the electrostatic charging issue of wafer probers
Fumiyoshi Furuhashi/Spansion
12:10-12:30
Authors' Interview Hours/Coffee Break
12:30-13:30
Lunch Time
13:30-15:30 Session 11 (Room A)
Process and Metrology Equipment (PE)
13:30-13:50 PE-82
Method for fast and accurate calibration of litho simulator for hot spot analysis
Youval Nehmadi /Applied Materials
13:50-14:10 PE-183
Recipe-independent Tool Health Indicator and Fault Prognosis
Argon Chen/National Taiwan University
14:10-14:30 PE-199
Non-Destructive Monitoring of Silicon Consumption During Shallow Trench Isolation Formation on 45nm Node Devices Using Spectroscopic Ellipsometry
Robert M. Peters/KLA-Tencor
14:30-14:50
Authors' Interview Hours/Coffee Break
11:10-12:30 Session 12 (Room B)
Manufacturing Strategy and Structure (MS)
11:10-11:30 MS-174
Using 'Locked Wafers' to Prioritize Factory Resources
John Pollock/Cypress Semiconductor
11:30-11:50 MS-251
Evolutionary Engineering Collaboration for DFM/DFY Solutions between Foundry and EDA Tools Vendor: A Preliminary Exploration
Yea-Huey Su/National Central University
11:50-12:10 MS-147
DFM Challenges for 32nm Node with Double Patterning Technology (DPT)
J. Fung Chen/ASML
12:10-12:30
Authors' Interview Hours/Coffee Break
12:30-13:30
Lunch Time
13:30-13:50 MS-252
Business Model Innovation with Effective Execution: An Exploratory Study on TSMC
Yea-Huey Su/National Central University
13:50-14:10 MS-169
APPROACH FOR A STANDARDISED METHODOLOGY FOR MULTI-SITE PROCESSING OF 300 MM WAFERS AT R&D-SITES
Richard Oechsner/Fraunhofer IISB
14:10-14:30 MS-173
Managing dynamic events in full-load states of semiconductor manufacturing chains
Yon-Chun Chou/National Taiwan University
14:30-14:50 MS-91
Monitor Cost Reduction through Application of Activity Based Costing
Chih-Wei Li/TSMC
14:50-15:10
Authors' Interview Hours/Coffee Break


Mon, Sep 25 | Tue, Sep 26 | Wed, Sep 27 | Interactive
14:50-17:10 Session 13 (Room A)
Summary Presentation for Interactive Poster Session Environment, Safety and Health (ES), Factory Design/Automated Material Handling (FD), Manufacturing Control and Execution (MC), Manufacturing Strategy and Structure (MS), Yeld Enhancement Methodology(YE)
14:50-15:00
Introduction of Interactive 3-minutes Talk Session
15:00-15:04 FD-189
TFT-LCD Automated Guided Vehicle Systems Analysis
Young Jae Jang/MIT
15:04-15:08 FD-208
Increased Fab Efficiency through the use of Small Lot Size FOUPs
Carl U. Buice, PhD/Asyst Technologies
15:08-15:12 ES-146
Development of Slow Start Safety Cylinder Valve to Inhibit Adiabatic Compression for Oxidized Gases
Takashi Orita/Taiyo Nippon Sanso Corporation
15:12-15:16 ES-154
Reduce VOC Emissions from Manufacturing Processes
TanLin Sheng/Intel
15:16-15:20 ES-254
Development and Practical Application of High-efficiency Fire Control System for the Clean Room
Soji Fukuda/Hitachi Plant Technologies, Ltd.
15:20-15:24 MC-201
Distributive and Cooperative Scheduling Considering Multi-Attribute Product-Mix,Feedback Processes,and the Dynamic Utility Control in Resource Sharing
Sumika Arima/University of Tsukuba
15:24-15:28 MC-163
Framework for Event Driven Sorter Operation
Ryuji Tamehiro/IBM
15:28-15:32 MC-152
Productivity improvement by integrated management of wafer map data
Norihiro.Takesako/Renesas Technology
15:32-15:36 MC-149
Support Vector based Demand Forecasting for Semiconductor Manufacturing
Prasanna Kumar Chittari/Intel
15:36-15:40 MC-170
Design of Segmented WIP Control for Cycle Time Reduction
Chen-Fu Chien/Department of Industrial Engineering and Engineering Management, National Tsing Hua University
15:40-15:44 MC-178
Priority Behavior Modeling of Fab for Supply Chain Management
Shi-Chung Chang/National Taiwan University
15:44-15:48 MC-55
Time Links Management Through Real-time Dispatch System
Chan Chih Ming/Chartered Semiconductor Manufacturing
15:48-15:52 MC-132
Systemic Operation Tracking Production-progress and Control Delivery to Reach Customer Satisfaction
Jui Feng Hung/Powerchip Semiconductor
15:52-15:56 MC-76
Integrated Production Control System in Managing Tool Uptime, Cycle-time and Capacity
Chan Chih Ming/Chartered Semiconductor Manufacturing
15:56-16:00 MC-233
Manufacturing Challenges for Double Patterning Lithography
William Arnold/Mircea Dusa/ASML
16:00-16:04 MC-223
Model Based Semiconductor Factory Automation for Rapid Factory Start Up and Change
Parris Hawkins/Applied Materials
16:04-16:08
Break
16:08-16:16 MS-74
Managing process constraint effectively to enable Fab cycle time reduction
HSU JUNG PIN/TSMC
16:16-16:20 MS-134
Study of the relation between Loading ratio and x-Factor
Satoru Tsuruta/NEC Electronics
16:20-16:24 MS-241
A Quadratic Goal Programming Model and Sensitivity Analysis for Semiconductor Supply Chain
David M. Chiang/National Taiwan University
16:24-16:28 MS-77
Parts Cost of Ownership Mechanism for Constantly Reducing Variable Cost of Equipment at Semiconductor Fabs
Hsin Jung Yang/UMC
16:28-16:32 YE-240
Nano-thickness stellar defects
Tsuyoshi Moriya/Tokyo Electron
16:32-16:36 YE-213
Novel Application of Programmed Defects to Enhance 200/300mm SEM Navigation Accuracy During 65nm MirrorBit™ Development
Stacy Sakai/Spansion
16:36-16:40 YE-98
Overall Wafer Effectiveness (OWE): A Novel Standard for Wafer Productivity
Chen-Fu Chien/TSMC
16:40-16:44 YE-207
Novel Use of Discrete SEM Inspection to Supplement and Refine Inline Defect Inspection During 65nm MirrorBit™ Development
Go Nagatani/Spansion
16:44-16:48 YE-96
Yield Methodology for Mixed Signal Process Development
Jin Liu/Texas Instruments
16:48-16:52 YE-73
The Optimization of Chamber Cleaning in the Etching Equipment
Teruo Yajima/Spansion
16:52-16:56 YE-140
A high resolution and early triggering method on multi layer processing defects
Chan Seong Choong/Systems on Silicon Manufacturing
16:56-17:00 YE-106
Investigation of post STI liner oxide annealing effect in 0.14um embedded flash technology
Jin Li Juan/Systems on Silicon Manufacturing
14:50-17:10 Session 14 (Room B)
Summary Presentation for Interactive Poster Session Process Control and Monitoring (PC), Process and Metrology Equipment (PE), Process and Materials Optimization (PO), Ultraclean Technology (UC)
14:50-15:00
Introduction of Interactive 3-minutes Talk Session
15:00-15:04 PC-1
Integrated ODP metrology as an APC enabler for complex high aspect ratio 3D deep trench device structures
Barbara Schmidt /Qimonda
15:04-15:08 PC-50
Threshold Voltage Asymmetry from Unintentional Angle of Implant on 90nm Floating Gate Flash Memory Devices
Arjun Rangarajan/Spansion
15:08-15:12 PC-141
Real-time monitoring of plasma flickering in high pressure electronegative discharge
Yongjin Kim/Samsung
15:12-15:16 PC-175
APC Methodology for Cpk improvement of HDP Deposition
Ramkumar Rajagopal/Intel
15:16-15:20 PC-162
Low-K CMP Process Control by using Interpolation Method.
Shigeki Kato/NEC Fabserve
15:20-15:24 PC-229
Utilization of insitu metrology capability of ASML Lithography Scanner to improve overall process control
Alek Chen/ASML
15:24-15:28 PC-203
Challenges of Manufacturing Capacitor Oxide in Mixed Signal ASICS
Janet Towner/AMI Semiconductor
15:28-15:32 PC-228
Real-time Monitoring of Photoresist Thickness Contour in Microlithography
Ho Weng Khuen/National University of Singapore
15:32-15:36 PC-137
Using product test data for manufacturing process control
Gerhard Spitzlsperger/Renesas Semiconductor Europe
15:36-15:40 PC-236
Samsung Equivalence Test for Output Parameters in Semiconductor Manufacturing
Ho Young Lee/Samsung
15:40-15:44 PC-232
ISMI Victory: Interface A Ready for Manufacturing
Harvey Wohlwend/International SEMATECH Manufacturing Initiative (ISMI)
15:44-16:05
Break
16:05-16:09 PE-145
Yield enhancement/Productivity improvement for Sub-110nm Memory Lithography using new alignment strategy
CI_Choi/SMIC
16:09-16:13 PE-86
A Technique for Discharge Stabilization Using an Ion Gauge
Tatsuo Muraoka/Fujitsu
16:13-16:17 PE-188
The ROI of Metrology
Benjamin Bunday/International Sematech
16:17-16:21 PO-253
Advantage of Siconi TM Preclean over Wet Clean for Pre Silicide Applications Beyond 65nm Node
Jianxin Lei /Applied Materials
16:21-16:25 PO-89
Improved CVD-Al Thin Film Using Superior Al Precursor
Seung-Min Ryu/Samsung
16:25-16:29 PO-160
Endpoint detection of dry cleaning on LPCVD Poly-Si process
Shinobu Asada/NEC Fabserve
16:29-16:33 PO-167
Use of Vertical Scanning Interferometry to Optimize HDP Oxide Thickness for STI CMP
Peter J. Beckage/Spansion
16:33-16:37 PO-78
Reliable High Volt Mixed Signal IC Manufacturing
John J. Naughton/AMI Semiconductor
16:37-16:41 PO-205
Development of SiN ESL for Cu BEOL of Advanced Flash Memory Devices
Minh-Van Ngo/Spansion
16:41-16:45 UC-157
A new air cleaning and cooling instrument usig oblique honeycomb
Satoshi Minobe/Nichias Corporation
16:45-16:49 UC-156
New QCM Sensor for Real-time AMC Detection in SMIF Pods
Ryozo Takasu/Fujitsu Laboratories Ltd.
16:49-16:53 UC-218
The Static Elimination System with Soft X-ray Air Ionizer Used in ULSI Cleanroom
Masafumi Sakuyama/Ibaraki University
16:53-16:57 UC-103
Inline VPD-TXRF for Contamination Control: Reality or Myth? Experience in a 300mm R&D Flash Memory Fab
Ercan Adem/Spansion
16:57-17:01 UC-161
The wafer preparation technology with nano size particle contamination by using single spin processor
Kousaku Matsuno/mFSI

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